On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

In this extended abstract, we summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA-based reconfgurable applicationspecific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and intetiace to application sofrware. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II [RuVi87]. Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on I10 modified industry benchmarks included with the Espresso II package. A more detailed discussion of this work is available